There has been hitherto known an A/D converter which is equipped with a ring gate delay circuit comprising inverting circuits connected to one another in a ring form as a high-resolution A/D converting circuit having no analog circuit portion, and uses variation of an inverting operation time of each inverting circuit in accordance with a power supply voltage (for example, JP-A-5-259907).
An A/D converting circuit disclosed in the above publication (hereinafter referred to as “time A/D converting circuit”) has been proposed by the applicant of this application, and the schematic construction thereof is shown in FIG. 8. As shown in FIG. 8, the time A/D converting circuit 100 comprises a pulse phase difference coding circuit 101 for encoding the phase difference of input pulses PA and PB, and a control circuit 102 for generating pulse signals PA and PB. The pulse phase difference coding circuit 101 comprises a ring gate delay circuit 110 which operates upon reception of the pulse signal PA from one input terminal and comprises one non-conjunction (NAND) circuit NAND as a starting inverting circuit and many inverters INV serving as inverting circuits which are linked to one another in a ring form, a counter 112 which is equipped at the front stage of the NAND circuit NAND in the ring gate delay circuit 110, and counting a round frequency of the pulse signal in the ring gate delay circuit 110 on the basis of the inversion frequency of the output level of the inverter INV to generate binary digital data, a latch circuit 114 for latching the digital data output from the counter 112, a pulse selector 116 for receiving the output of each of the inverting circuits (that is, the NAND circuit NAND and the inverters INV) constituting the ring gate delay circuit 110, extracting a pulse signal which is rounding through the ring gate delay circuit 110 from the output level thereof, and generating a signal representing the position of the pulse signal concerned, an encoder 118 for generating digital data corresponding to the output signal from the pulse selector 116, a signal processing circuit 119 which receives digital data from the latch circuit 114 as upper bits and digital data from the encoder 118 as lower bits to generate binary digital data d representing the phase difference between the pulse signals PA and PB, and a data output line 120 for outputting the digital data d generated in the signal processing circuit 119 to the external. The latch circuit 114 and the pulse selector 116 operate upon reception of the pulse signal PB output from the control circuit 102.
In the pulse phase difference coding circuit 101 thus constructed, when the pulse signal PA output from a control circuit 102 is set to High level, the ring gate delay circuit 110 starts the rounding operation of the pulse signal, and makes the pulse signal round while the pulse signal PA is set to High level. The round frequency is counted by the counter 112, and the count result is latched by the latch circuit 114 at the time point when the pulse signal PB output from the control circuit 102 is set to High level.
When the pulse signal PB output from the control circuit 102 is set to High level, the pulse selector 116 detects the round position of the pulse signal in the ring gate delay circuit 110, and the encoder 118 generates digital data corresponding to the round position. At this time, the signal processing circuit 119 generates binary digital data d corresponding to the time Tc from the rise-up of the pulse signal PA till the rise-up of the pulse signal PB on the basis of the digital data from the encoder 118 and the digital data latched in the latch circuit 114, and outputs the binary digital data d thus generated through a data output line 120 to the external.
Furthermore, an input terminal 101a for an analog signal (voltage signal) Vin to be A/D-converted is connected to a power supply line 110a for supplying power to each of the inverting circuits (that is, the NAND circuit NAND and the inverters INV) in the ring gate delay circuit 110, and the analog signal Vin is applied as a power supply voltage to each inverting circuit.
The inverting operation time (that is, the delay time of the pulse signal) in each inverting circuit is varied with the power supply voltage, so that the digital data d output from the data output line 120 is varied in accordance with the voltage level of the analog signal Vin. If the time Tc is fixed, the digital data corresponding to the analog signal Vin could be achieved. Therefore, in the time A/D converting circuit 100, the control circuit 102 is designed so that the time Tc from the rise-up of the pulse signal PA till the rise-up of the pulse signal PB is set to a fixed time at all times.
As a result, according to the time A/D converting circuit 100, the digital data d corresponding to the analog signal Vin is output from the pulse phase difference coding circuit 101, and also the A/D converting operation thereof is periodically carried out in conformity with the output period of the pulse signals PA, PB of the control circuit 102, so that the digital data d varies periodically in conformity with the variation of the analog signal Vin.
In the time A/D converting circuit 100 thus constructed, the characteristic of the digital data d with respect to the analog signal Vin has non-linearity as shown in FIG. 6. The reason why the A/D conversion output data (digital data d) does not linearly vary with respect to the variation of the analog signal Vin resides in that the delay time of each of the NAND circuit NAND and the inverters INV which constitute the ring gate delay circuit 110 does not vary in proportion to the variation of the power supply voltage.
Furthermore, in the time A/D conversion circuit 100 thus constructed, the analog signal Vin is also normally applied as a driving voltage to other circuits as well as the ring gate delay circuit 110, that is, the overall pulse phase difference coding circuit 101 to operate these circuits. Therefore, delay times caused by operations in the other circuits than the ring gate delay circuit 110 are varied by an effect of the analog signal Vin. These delay times do not vary in proportional to the variation of the analog signal Vin as the power supply voltage.
Therefore, in the time A/D converting circuit 100, the characteristic of the digital data d with respect to the analog signal Vin (hereinafter referred to as “A/D conversion output characteristic”) has relatively large non-linearity. The time A/D converting circuit 100 having such non-linearity induces a problem in sensing equipment, etc. to which precise linearity is required, and it is difficult to use the A/D converting circuit described above in sensing equipment, measuring equipment, etc.
Therefore, JP-A-5-259907 discloses a method for linearly correcting non-linearity of the A/D conversion output characteristic. According to this linearly correcting method, ROM in which correcting data are stored is prepared, and correction values are allocated to the A/D conversion output data in one-to-one correspondence, thereby performing linear correction.
Furthermore, a correcting method of applying a fixed voltage different from the analog signal Vin to the other circuits than the ring gate delay circuit 110 to operate the other circuits, thereby reducing the non-linearity error (see JP-A-2002-118467) has been proposed for the power supply method of applying the analog signal Vin to the overall pulse phase difference coding circuit 101 as a driving voltage to operate the elements constituting the pulse phase difference coding circuit 101 as described above.
According to the correcting method proposed in JP-A-2002-118467, the non-linearity error caused by application of the analog signal Vin corresponding to A/D conversion target as a driving voltage to the other circuits than the ring gate delay circuit 110 is vanished, and thus the non-linearity error can be reduced to some extent. However, a non-linearity error caused by the fact that the pulse delay time in the ring gate delay circuit 110 is not proportional to the power supply voltage remains. Therefore, there is a problem that high-precision A/D conversion cannot be performed.
Furthermore, the linear correction method disclosed in JP-A-5-259907 can theoretically perform the linear correction on the non-linear error substantially perfectly. However, it is required to prepare for a large-capacity ROM and store vast amounts of correction values in the ROM. In addition, the A/D conversion output characteristic has a characteristic varying with temperature variation. That is, the delay time of each of the inverting circuits constituting the ring gate delay circuit 110 varies not only with the analog signal Vin as the power supply voltage, but also with temperature. Therefore, the non-linearity of the A/D conversion output characteristic is varied with temperature.
In order to take a countermeasure to the foregoing problem, there may be considered a method of separately equipping a temperature measuring circuit and also storing correction values dependent on temperature in a correcting ROM to thereby perform correction in consideration of the temperature characteristic. However, this method needs to prepare correction values for each of plural temperatures in an estimated temperature range, resulting in increase in scale of ROM and complication of the circuit construction. Therefore, the cost is increased and thus this method is not practical.
Furthermore, not only in the time A/D converting circuit 100, but also in a general A/D converting circuit having an analog circuit (for example, a double integral type), a non-linearity error is generally contained in the A/D conversion output data. In addition, a temperature drift in which an output value is varied by variation of the ambient temperature occurs. Therefore, even when the method using the correcting ROM as described above is applied as a method of correcting non-linearity of a general A/D converting circuit, the same problem (cost-up due to increase of scale of ROM, etc.) occurs and thus this method is not practical.